1. Field of the Invention
The present invention relates to non-volatile memory devices and method of manufacturing the same. More particularly, the present invention relates to a multi-bit non-volatile memory device having a dual gate structure, and method of manufacturing the same, and an operating method for a multi-bit cell operation.
2. Discussion of Related Art
A flash memory, i.e., a non-volatile memory device in which data can be electrically programmed/erased/read can be higher integrated and have a superior data integrity. Therefore, the flash memory can be used as an auxiliary memory of a system and can also be applied to DRAM interface.
The flash memory has been designed toward a direction in which the level of integration is increased and the size is miniaturized. However, in the case where a device structure of an existing 2 dimensional channel is employed, a short channel effect, such as an increase in the leakage current, is generated when the device size shrinks. Accordingly, a problem arises because the integration is limited. To reduce the short channel effect, 30 nm grade triple gate non-volatile memory cells employing a multi gate pin FET structure, a charge trapping type structure, such as MNOS (Metal Nitride Oxide Semiconductor) and MONOS (Metal Oxide Nitride Oxide Semiconductor), and a SONOS (Poly-Silicon Oxide Nitride Oxide Semiconductor) structure was fabricated. However, there is a problem in that the related art gate structures do not sufficiently reduce the short channel effect.
Furthermore, the related art triple gate non-volatile memory cells operate 1-bit. Accordingly, there is an urgent need for multi-bit techniques in which 2-bit or more data can be stored per cell in order to lower the cost per bit and increase the degree of integration. In other words, for the purpose of higher integration of the memory, there is a need for a gate structure capable of reducing the short channel effect and a multi-bit structure capable of storing 2-bit or more data.